The present invention relates to a method and apparatus for disabling and restarting a clock in a device. The invention is particularly directed to devices requiring the suppression of clock generation in periods of inactivity to reduce power consumption, such as battery powered devices.
In battery powered products, such as mobile phones or portable personal computers, it is important to save power in order to prolong the lifetime of the batteries. One way of reducing power is to switch off clocks to processors in periods of inactivity. However, in products wherein synchronised operation with an external device is required, such as mobile phones which must be synchronised with a network, for example, at least one clock must be running constantly to provide this synchronisation. In products incorporating several processors, one processor is generally designated as a master processor to one or several slave processors in the product, and will control the switching on and off of clock signals to these slave processors when required. However, in order to restart a clock, the master processor must be aware of any event, such as the pressing of a key on a mobile phone, which requires the synchronised operation of a slave processor, and therefore the supply of the clock signal, to be restarted.
In a clock control arrangement described in JP 7-244650 an external clock source is provided to a digital signal processor of a digital radio terminal. The arrangement generates an internal clock from the external clock signal, but supply of the external clock may be suppressed in periods of inactivity to save power. This is managed using a clock control signal emitted by the clock control arrangement. While this signal is high, the external clock signal is supplied to the processor. When a low power mode, or sleep mode, is set by software, the clock request signal emitted by the clock control arrangement is forced low. The supply of the external clock is then suppressed and the internal clock halted. When an interruption request, indicating the need for a clock signal, is received by the clock control arrangement, the clock request signal is set high, whereupon the internal clock is enabled and the external clock is supplied again.
A problem with this arrangement is that the arrival of an asynchronous interrupt at the moment of suppressing the external clock may cause the internal clock to toggle and possibly cause the processor circuitry to enter a prohibited state. Furthermore, the state of the restarted internal clock is uncertain since it is dependent on the retransmission of the external clock in response to an asynchronous request. A further drawback of the described arrangement is that the clock control device can deal with only one interrupt, which severely limits its applications.
It is therefore an object of the present invention to provide a method and apparatus for clock control, which overcomes the problems associated with the prior art.
It is a specific object of the present invention to provide a method and apparatus for clock control which enables an internal clock signal to be stopped reliably and cleanly and also to be restarted reliably and cleanly in response to an asynchronous event.
These and further objects are achieved in an apparatus for controlling a clock having switching means for switching an external clock through to the device as an internal clock, and clock request generation means, adapted to transmit request signals to an external clock controller. These signals serve as requests to suppress and restart the external clock. Control means are provided to control the generation of the internal clock through the switching means and the clock request generation means in accordance with the predetermined state of at least one control signal. The clock request generation means are also coupled to a clock start module adapted to receive several input signals that may signal an event requiring the clocked operation of the device. Preferably, the control means control clock suppression and restarting using two signals, one originating in the device, the other in the clock control means. On entering a low power mode, the internal clock is first disabled, then a request for suppression of the external clock sent. This provides the conditions for the external clock to be disabled, unless one of the input signals changes state, which effectively causes the request to be suppressed. The external clock thus remains in operation, so allowing the internal clock to be restarted cleanly.
With this apparatus, the control of the internal clock may be separate from, and independent of, any request to stop or restart the external clock. Hence the internal clock can be cleanly and reliably stopped and restarted under control of the external clock, even in the event of an asynchronous request for clocked operation. Furthermore, a clock request signal resulting from a change of state of any input signal can be controlled by the arrangement such that it prevents the suppression of the external clock or initiates the restarting of the external clock as appropriate. A single request signal may be generated from any of several input signals, while the use of one or only two signals to control the external clock means that, at most, only two connections need be provided between the device and the external clock controller for controlling clock generation, irrespective of the number of input signals.